The present invention relates to a semiconductor integrated circuit device and relates in particular to a semiconductor integrated circuit device with excellent high speed and low power operation characteristics.
As the chip manufacturing process progresses towards making smaller and finer chip circuitry, the different leakage currents within the chip, including the subthreshold leakage current, gate tunneling leakage current and GIDL (Gate-Induced Drain Leakage) current increase as described in xe2x80x9cIdentifying defects in deep-submicron CMOS ICsxe2x80x9d, IEEE Spectrum, pp. 66-71, September, 1996 (hereafter referred to as reference 1). These leakage currents increase the electrical current consumption of the chip.
A method for reducing subthreshold leakage current in the related art is disclosed in xe2x80x9cA Low Power Data Holding Circuit with an Intermittent Power Supply Schemexe2x80x9d, Symposium on VLSI Circuits Digest of Technical Papers, pp. 14-15, 1996 (hereafter referred to as reference 2). In the method of reference 2, a power switch composed of MOS transistors having a threshold voltage with an absolute value sufficiently higher than the absolute values of threshold voltages of MOS transistors comprising the circuit block, is inserted in series with the circuit block power supply between power and ground. Here, the term MOS transistor is used in these specifications as a general term to describe an insulated gate type field effect transistor. Also, the power supply voltage supplied to the circuit is defined as having a high voltage (potential) and low voltage (potential). However, this is used here to respectively express the power supply as the high voltage potential and the ground as the low voltage potential. While the chip is in standby (idle), the subthreshold leakage current flowing through the circuit block is cut off by turning this power switch off. Usually, setting this power switch to off, erases the information stored in the information retention circuits (in circuits with a volatile information holding function for example; static memories, flip-flops, latches and register files, etc.) within the circuit block because the supply of power to the circuit blocks is cut off. In fact however, a particular time (TR) is required before the information within the information retention circuits is erased after setting the power switch to off. The method in reference 2 therefore turns the power switch on once again before the time TR elapses after the power switch was turned off (Hereafter, the operation of turning the power supply on once again is called the refresh operation.) Then, the power supply switch is turned off after a fixed amount of time, and this process is repeated to prevent information within the information retention circuit from being erased and to reduce the amount of current consumption in the circuit block due to subthreshold leakage current.
A method disclosed in xe2x80x9cA Novel Powering-down Scheme for Low Vt CMbS Circuitsxe2x80x9d, Symposium on VLSI Circuits Digest of Technical Papers, pp. 44-45, 1998 (hereafter referred to as reference 3) has the same power switch and circuit block connections as in reference 2. In the method of reference 3, a diode is connected in series with the power switch to clamp (reduce) to a lower level the excess voltage (voltage differential between power and ground) supplied to the circuit block while the power switch is on and prevent the loss of information from information retention circuits in the circuit block. In the figures given in the example in reference 3, the voltage differential of the power supplied to the circuit block while the power switch is off is 0.7 or more volts and is the threshold voltage (PMOS is xe2x88x920.14 volts and NMOS is 0.31 volts) of the MOS transistor comprising the circuit block.
The power switch is composed of MOS transistors having a threshold voltage of a sufficiently high absolute value. In the method of reference 2, the power switch is repeatedly turned on and off while the chip is in a standby (idle) state, and the node within the circuit block are repeatedly discharged. Large-size MOS transistors are generally used in the power switch to prevent a loss in speed from occurring during the circuit block operation. The parasitic capacitance of all nodes of the circuit block is also dependent on the circuit scale (integration) and may at times exceed several nanofarads. The repeated turning of the power switch on and off as well as the repeated discharging of the node within the block circuit therefore increase the chip current consumption.
In the method of reference 3 on the other hand, the voltage (voltage differential between power and ground) supplied to the circuit block when the power switch is off is larger than the absolute value of the MOS transistor threshold voltage (PMOS is xe2x88x920.14 volts and NMOS is 0.31 volts).
Noticing the fact that the information in the information retention circuit can still be retained even if the supply voltage when the power supply switch was off is made lower than absolute value of the MOS transistor threshold voltage, the inventors developed a structure capable of retaining information in the information retention circuit and reducing electrical power loss due to leakage (current).
To resolve the above mentioned problems with the related art, in a typical embodiment of the invention, a semiconductor integrated circuit device comprising a circuit block having a first MOS transistor, and a leakage current control circuit having a second MOS transistor and a current source; a source and drain circuit of the second MOS transistor is formed between the power supply line of the circuit block and voltage potential point where the operating voltage is supplied. This current source is connected to the power supply line, and in a first state the power supply line is driven to a first voltage by the second MOS transistor and, in a second state, the power supply line is controlled at a second voltage by current flow in the current source. The voltage applied across the source and drain of the first MOS transistor in the second state is smaller than the voltage applied across the source and drain of the first MOS transistor in the first state.
The present invention is therefore capable of reducing the different types of leakage current (subthreshold leakage current, GIDL current, gate tunneling current, etc.) while the circuit block is in standby state while still maintaining the information stored in the information retention circuits within the circuit block. The present invention also allows high speed circuit block operation while the circuit block is in the operation state.